documentation:examples:ibm_system_x3550_m3
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— | documentation:examples:ibm_system_x3550_m3 [2013/09/19 22:20] (current) – created - external edit 127.0.0.1 | ||
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+ | ====== IBM System x3550 M3 ====== | ||
+ | ==== dmesg ==== | ||
+ | |||
+ | < | ||
+ | Copyright (c) 1992-2013 The FreeBSD Project. | ||
+ | Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 | ||
+ | The Regents of the University of California. All rights reserved. | ||
+ | FreeBSD is a registered trademark of The FreeBSD Foundation. | ||
+ | FreeBSD 9.2-RC4 #0 r255473M: Sat Sep 14 22:53:03 CEST 2013 | ||
+ | root@orange.bsdrp.net:/ | ||
+ | gcc version 4.2.1 20070831 patched [FreeBSD] | ||
+ | CPU: Intel(R) Xeon(R) CPU | ||
+ | Origin = " | ||
+ | Features=0xbfebfbff< | ||
+ | Features2=0x29ee3ff< | ||
+ | AMD Features=0x2c100800< | ||
+ | AMD Features2=0x1< | ||
+ | TSC: P-state invariant, performance statistics | ||
+ | real memory | ||
+ | avail memory = 16475496448 (15712 MB) | ||
+ | Event timer " | ||
+ | ACPI APIC Table: < | ||
+ | FreeBSD/ | ||
+ | FreeBSD/ | ||
+ | cpu0 (BSP): APIC ID: 0 | ||
+ | cpu1 (AP): APIC ID: 2 | ||
+ | cpu2 (AP): APIC ID: 18 | ||
+ | cpu3 (AP): APIC ID: 20 | ||
+ | ACPI Warning: Invalid length for Pm1aControlBlock: | ||
+ | ioapic0 <Version 2.0> irqs 0-23 on motherboard | ||
+ | ioapic1 <Version 2.0> irqs 24-47 on motherboard | ||
+ | netmap: loaded module | ||
+ | cryptosoft0: | ||
+ | acpi0: <IBM THURLEY> on motherboard | ||
+ | acpi0: Power Button (fixed) | ||
+ | Timecounter " | ||
+ | Event timer " | ||
+ | Event timer " | ||
+ | Event timer " | ||
+ | Event timer " | ||
+ | cpu0: <ACPI CPU> on acpi0 | ||
+ | cpu1: <ACPI CPU> on acpi0 | ||
+ | cpu2: <ACPI CPU> on acpi0 | ||
+ | cpu3: <ACPI CPU> on acpi0 | ||
+ | atrtc0: <AT realtime clock> port 0x70-0x77 irq 8 on acpi0 | ||
+ | atrtc0: Warning: Couldn' | ||
+ | Event timer " | ||
+ | attimer0: <AT timer> port 0x40-0x43, | ||
+ | Timecounter " | ||
+ | Event timer " | ||
+ | Timecounter " | ||
+ | acpi_timer0: | ||
+ | pcib0: <ACPI Host-PCI bridge> port 0xcf8-0xcff on acpi0 | ||
+ | pcib0: Length mismatch for 3 range: 1 vs 8100000000 | ||
+ | pci0: <ACPI PCI bus> on pcib0 | ||
+ | pcib1: <ACPI PCI-PCI bridge> irq 28 at device 1.0 on pci0 | ||
+ | pci11: <ACPI PCI bus> on pcib1 | ||
+ | bce0: < | ||
+ | miibus0: <MII bus> on bce0 | ||
+ | brgphy0: <BCM5709 10/ | ||
+ | brgphy0: | ||
+ | bce0: Ethernet address: 5c: | ||
+ | bce0: ASIC (0x57092003); | ||
+ | Coal (RX: | ||
+ | bce1: < | ||
+ | miibus1: <MII bus> on bce1 | ||
+ | brgphy1: <BCM5709 10/ | ||
+ | brgphy1: | ||
+ | bce1: Ethernet address: 5c: | ||
+ | bce1: ASIC (0x57092003); | ||
+ | Coal (RX: | ||
+ | pcib2: <PCI-PCI bridge> irq 29 at device 2.0 on pci0 | ||
+ | pci16: <PCI bus> on pcib2 | ||
+ | pcib3: <ACPI PCI-PCI bridge> irq 24 at device 3.0 on pci0 | ||
+ | pci21: <ACPI PCI bus> on pcib3 | ||
+ | ix0: < | ||
+ | ix0: Using MSIX interrupts with 5 vectors | ||
+ | ix0: Ethernet address: a0: | ||
+ | ix0: PCI Express Bus: Speed 5.0GT/s Width x8 | ||
+ | 001.000007 netmap_attach [1696] success for ix0 | ||
+ | ix1: < | ||
+ | ix1: Using MSIX interrupts with 5 vectors | ||
+ | ix1: Ethernet address: a0: | ||
+ | ix1: PCI Express Bus: Speed 5.0GT/s Width x8 | ||
+ | 001.000008 netmap_attach [1696] success for ix1 | ||
+ | pcib4: <ACPI PCI-PCI bridge> irq 30 at device 7.0 on pci0 | ||
+ | pci26: <ACPI PCI bus> on pcib4 | ||
+ | igb0: < | ||
+ | igb0: Using MSIX interrupts with 5 vectors | ||
+ | igb0: Ethernet address: 00: | ||
+ | igb0: Bound queue 0 to cpu 0 | ||
+ | igb0: Bound queue 1 to cpu 1 | ||
+ | igb0: Bound queue 2 to cpu 2 | ||
+ | igb0: Bound queue 3 to cpu 3 | ||
+ | 001.000009 netmap_attach [1696] success for igb0 | ||
+ | igb1: < | ||
+ | igb1: Using MSIX interrupts with 5 vectors | ||
+ | igb1: Ethernet address: 00: | ||
+ | igb1: Bound queue 0 to cpu 0 | ||
+ | igb1: Bound queue 1 to cpu 1 | ||
+ | igb1: Bound queue 2 to cpu 2 | ||
+ | igb1: Bound queue 3 to cpu 3 | ||
+ | 001.000010 netmap_attach [1696] success for igb1 | ||
+ | igb2: < | ||
+ | igb2: Using MSIX interrupts with 5 vectors | ||
+ | igb2: Ethernet address: 00: | ||
+ | igb2: Bound queue 0 to cpu 0 | ||
+ | igb2: Bound queue 1 to cpu 1 | ||
+ | igb2: Bound queue 2 to cpu 2 | ||
+ | igb2: Bound queue 3 to cpu 3 | ||
+ | 001.000011 netmap_attach [1696] success for igb2 | ||
+ | igb3: < | ||
+ | igb3: Using MSIX interrupts with 5 vectors | ||
+ | igb3: Ethernet address: 00: | ||
+ | igb3: Bound queue 0 to cpu 0 | ||
+ | igb3: Bound queue 1 to cpu 1 | ||
+ | igb3: Bound queue 2 to cpu 2 | ||
+ | igb3: Bound queue 3 to cpu 3 | ||
+ | 001.000012 netmap_attach [1696] success for igb3 | ||
+ | pci0: <base peripheral, interrupt controller> | ||
+ | pci0: <base peripheral, interrupt controller> | ||
+ | pci0: <base peripheral, interrupt controller> | ||
+ | pci0: <base peripheral, interrupt controller> | ||
+ | pci0: <base peripheral, interrupt controller> | ||
+ | pci0: <base peripheral, interrupt controller> | ||
+ | pci0: <base peripheral, interrupt controller> | ||
+ | pci0: <base peripheral, interrupt controller> | ||
+ | pci0: <base peripheral> | ||
+ | pci0: <base peripheral> | ||
+ | pci0: <base peripheral> | ||
+ | pci0: <base peripheral> | ||
+ | pci0: <base peripheral> | ||
+ | pci0: <base peripheral> | ||
+ | pci0: <base peripheral> | ||
+ | pci0: <base peripheral> | ||
+ | uhci0: <Intel 82801JI (ICH10) USB controller USB-D> port 0x20a0-0x20bf irq 17 at device 26.0 on pci0 | ||
+ | usbus0 on uhci0 | ||
+ | uhci1: <Intel 82801JI (ICH10) USB controller USB-E> port 0x2080-0x209f irq 18 at device 26.1 on pci0 | ||
+ | usbus1 on uhci1 | ||
+ | ehci0: <Intel 82801JI (ICH10) USB 2.0 controller USB-B> mem 0x97d21000-0x97d213ff irq 19 at device 26.7 on pci0 | ||
+ | usbus2: EHCI version 1.0 | ||
+ | usbus2 on ehci0 | ||
+ | pcib5: <ACPI PCI-PCI bridge> irq 16 at device 28.0 on pci0 | ||
+ | pci1: <ACPI PCI bus> on pcib5 | ||
+ | mpt0: < | ||
+ | mpt0: MPI Version=1.5.20.0 | ||
+ | mpt0: Capabilities: | ||
+ | mpt0: 1 Active Volume (2 Max) | ||
+ | mpt0: 2 Hidden Drive Members (14 Max) | ||
+ | pcib6: <PCI-PCI bridge> irq 16 at device 28.4 on pci0 | ||
+ | pci6: <PCI bus> on pcib6 | ||
+ | pcib7: <PCI-PCI bridge> irq 16 at device 0.0 on pci6 | ||
+ | pci7: <PCI bus> on pcib7 | ||
+ | vgapci0: < | ||
+ | uhci2: <Intel 82801JI (ICH10) USB controller USB-A> port 0x2060-0x207f irq 17 at device 29.0 on pci0 | ||
+ | usbus3 on uhci2 | ||
+ | uhci3: <Intel 82801JI (ICH10) USB controller USB-B> port 0x2040-0x205f irq 18 at device 29.1 on pci0 | ||
+ | usbus4 on uhci3 | ||
+ | uhci4: <Intel 82801JI (ICH10) USB controller USB-C> port 0x2020-0x203f irq 19 at device 29.2 on pci0 | ||
+ | usbus5 on uhci4 | ||
+ | ehci1: <Intel 82801JI (ICH10) USB 2.0 controller USB-A> mem 0x97d20000-0x97d203ff irq 17 at device 29.7 on pci0 | ||
+ | usbus6: EHCI version 1.0 | ||
+ | usbus6 on ehci1 | ||
+ | pcib8: <PCI-PCI bridge> at device 30.0 on pci0 | ||
+ | pci31: <PCI bus> on pcib8 | ||
+ | isab0: <PCI-ISA bridge> at device 31.0 on pci0 | ||
+ | isa0: <ISA bus> on isab0 | ||
+ | atapci0: <Intel ICH10 SATA300 controller> | ||
+ | ata2: <ATA channel> at channel 0 on atapci0 | ||
+ | ata3: <ATA channel> at channel 1 on atapci0 | ||
+ | pci0: <serial bus, SMBus> at device 31.3 (no driver attached) | ||
+ | atapci1: <Intel ICH10 SATA300 controller> | ||
+ | ata4: <ATA channel> at channel 0 on atapci1 | ||
+ | ata5: <ATA channel> at channel 1 on atapci1 | ||
+ | uart0: <16550 or compatible> | ||
+ | uart1: <16550 or compatible> | ||
+ | qpi0: <QPI system bus> on motherboard | ||
+ | pcib9: <QPI Host-PCI bridge> pcibus 255 on qpi0 | ||
+ | pci255: <PCI bus> on pcib9 | ||
+ | orm0: <ISA Option ROM> at iomem 0xc0000-0xc7fff on isa0 | ||
+ | sc0: <System console> at flags 0x100 on isa0 | ||
+ | sc0: VGA <16 virtual consoles, flags=0x300> | ||
+ | vga0: <Generic ISA VGA> at port 0x3c0-0x3df iomem 0xa0000-0xbffff on isa0 | ||
+ | atkbdc0: < | ||
+ | atkbd0: <AT Keyboard> | ||
+ | atkbd0: [GIANT-LOCKED] | ||
+ | est0: < | ||
+ | est: CPU supports Enhanced Speedstep, but is not recognized. | ||
+ | est: cpu_vendor GenuineIntel, | ||
+ | device_attach: | ||
+ | p4tcc0: <CPU Frequency Thermal Control> on cpu0 | ||
+ | est1: < | ||
+ | est: CPU supports Enhanced Speedstep, but is not recognized. | ||
+ | est: cpu_vendor GenuineIntel, | ||
+ | device_attach: | ||
+ | p4tcc1: <CPU Frequency Thermal Control> on cpu1 | ||
+ | est2: < | ||
+ | est: CPU supports Enhanced Speedstep, but is not recognized. | ||
+ | est: cpu_vendor GenuineIntel, | ||
+ | device_attach: | ||
+ | p4tcc2: <CPU Frequency Thermal Control> on cpu2 | ||
+ | est3: < | ||
+ | est: CPU supports Enhanced Speedstep, but is not recognized. | ||
+ | est: cpu_vendor GenuineIntel, | ||
+ | device_attach: | ||
+ | p4tcc3: <CPU Frequency Thermal Control> on cpu3 | ||
+ | Timecounters tick every 1.000 msec | ||
+ | IPsec: Initialized Security Association Processing. | ||
+ | usbus0: 12Mbps Full Speed USB v1.0 | ||
+ | usbus1: 12Mbps Full Speed USB v1.0 | ||
+ | usbus2: 480Mbps High Speed USB v2.0 | ||
+ | usbus3: 12Mbps Full Speed USB v1.0 | ||
+ | usbus4: 12Mbps Full Speed USB v1.0 | ||
+ | usbus5: 12Mbps Full Speed USB v1.0 | ||
+ | usbus6: 480Mbps High Speed USB v2.0 | ||
+ | ugen0.1: < | ||
+ | uhub0: <Intel UHCI root HUB, class 9/0, rev 1.00/1.00, addr 1> on usbus0 | ||
+ | ugen1.1: < | ||
+ | uhub1: <Intel UHCI root HUB, class 9/0, rev 1.00/1.00, addr 1> on usbus1 | ||
+ | ugen2.1: < | ||
+ | uhub2: <Intel EHCI root HUB, class 9/0, rev 2.00/1.00, addr 1> on usbus2 | ||
+ | ugen3.1: < | ||
+ | uhub3: <Intel UHCI root HUB, class 9/0, rev 1.00/1.00, addr 1> on usbus3 | ||
+ | ugen4.1: < | ||
+ | uhub4: <Intel UHCI root HUB, class 9/0, rev 1.00/1.00, addr 1> on usbus4 | ||
+ | ugen5.1: < | ||
+ | uhub5: <Intel UHCI root HUB, class 9/0, rev 1.00/1.00, addr 1> on usbus5 | ||
+ | ugen6.1: < | ||
+ | uhub6: <Intel EHCI root HUB, class 9/0, rev 2.00/1.00, addr 1> on usbus6 | ||
+ | uhub0: 2 ports with 2 removable, self powered | ||
+ | uhub1: 2 ports with 2 removable, self powered | ||
+ | uhub3: 2 ports with 2 removable, self powered | ||
+ | uhub4: 2 ports with 2 removable, self powered | ||
+ | uhub5: 2 ports with 2 removable, self powered | ||
+ | mpt0: mpt_read_cfg_page: | ||
+ | mpt0: | ||
+ | mpt0: | ||
+ | mpt0: | ||
+ | mpt0: | ||
+ | (mpt0:0:4): Physical (mpt0: | ||
+ | (mpt0:0:4): Online | ||
+ | (mpt0:0:5): Physical (mpt0: | ||
+ | (mpt0:0:5): Online | ||
+ | pass1 at ata2 bus 0 scbus2 target 0 lun 0 | ||
+ | da0 at mpt0 bus 0 scbus0 target 3 lun 0 | ||
+ | da0: < | ||
+ | da0: 300.000MB/s transfers | ||
+ | da0: Command Queueing enabled | ||
+ | da0: 33378MB (68358144 512 byte sectors: 255H 63S/T 4255C) | ||
+ | pass1: < | ||
+ | pass1: 150.000MB/s transfers (SATA 1.x, UDMA2, ATAPI 12bytes, PIO 8192bytes) | ||
+ | SMP: AP CPU #1 Launched! | ||
+ | SMP: AP CPU #2 Launched! | ||
+ | SMP: AP CPU #3 Launched! | ||
+ | Timecounter " | ||
+ | Trying to mount root from ufs:/ | ||
+ | ugen3.2: <IBM> at usbus3 | ||
+ | ichsmb0: <Intel 82801JI (ICH10) SMBus controller> | ||
+ | smbus0: <System Management Bus> on ichsmb0 | ||
+ | coretemp0: <CPU On-Die Thermal Sensors> on cpu0 | ||
+ | est0: < | ||
+ | est: CPU supports Enhanced Speedstep, but is not recognized. | ||
+ | est: cpu_vendor GenuineIntel, | ||
+ | device_attach: | ||
+ | coretemp1: <CPU On-Die Thermal Sensors> on cpu1 | ||
+ | est1: < | ||
+ | est: CPU supports Enhanced Speedstep, but is not recognized. | ||
+ | est: cpu_vendor GenuineIntel, | ||
+ | device_attach: | ||
+ | coretemp2: <CPU On-Die Thermal Sensors> on cpu2 | ||
+ | est2: < | ||
+ | est: CPU supports Enhanced Speedstep, but is not recognized. | ||
+ | est: cpu_vendor GenuineIntel, | ||
+ | device_attach: | ||
+ | coretemp3: <CPU On-Die Thermal Sensors> on cpu3 | ||
+ | est3: < | ||
+ | est: CPU supports Enhanced Speedstep, but is not recognized. | ||
+ | est: cpu_vendor GenuineIntel, | ||
+ | device_attach: | ||
+ | aesni0: < | ||
+ | </ | ||
+ | |||
+ | ==== pciconf ==== | ||
+ | |||
+ | < | ||
+ | hostb0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 05[60] = MSI supports 2 messages, vector masks | ||
+ | cap 10[90] = PCI-Express 2 root port max data 128(128) link x4(x4) | ||
+ | speed 2.5(2.5) ASPM disabled(L0s/ | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D0 | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 0 corrected | ||
+ | ecap 000d[150] = ACS 1 | ||
+ | ecap 000b[160] = Vendor 0 | ||
+ | pcib1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 0d[40] = PCI Bridge card=0x34081014 | ||
+ | cap 05[60] = MSI supports 2 messages, vector masks | ||
+ | cap 10[90] = PCI-Express 2 root port max data 256(256) link x2(x2) | ||
+ | speed 5.0(5.0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D0 | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 0 corrected | ||
+ | ecap 000d[150] = ACS 1 | ||
+ | ecap 000b[160] = Vendor 0 | ||
+ | pcib2@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 0d[40] = PCI Bridge card=0x34091014 | ||
+ | cap 05[60] = MSI supports 2 messages, vector masks | ||
+ | cap 10[90] = PCI-Express 2 root port max data 256(256) link x0(x2) | ||
+ | speed 0.0(5.0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D0 | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 0 corrected | ||
+ | ecap 000d[150] = ACS 1 | ||
+ | pcib3@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 0d[40] = PCI Bridge card=0x340a1014 | ||
+ | cap 05[60] = MSI supports 2 messages, vector masks | ||
+ | cap 10[90] = PCI-Express 2 root port slot max data 256(256) link x8(x16) | ||
+ | speed 5.0(5.0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D0 | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 0 corrected | ||
+ | ecap 000d[150] = ACS 1 | ||
+ | ecap 000b[160] = Vendor 0 | ||
+ | pcib4@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 0d[40] = PCI Bridge card=0x340e1014 | ||
+ | cap 05[60] = MSI supports 2 messages, vector masks | ||
+ | cap 10[90] = PCI-Express 2 root port slot max data 256(256) link x4(x16) | ||
+ | speed 5.0(5.0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D0 | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 0 corrected | ||
+ | ecap 000d[150] = ACS 1 | ||
+ | ecap 000b[160] = Vendor 0 | ||
+ | none0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | cap 09[50] = vendor (length 255) Intel cap 15 version 0 | ||
+ | none1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | none2@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | cap 09[50] = vendor (length 255) Intel cap 15 version 0 | ||
+ | none3@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | none4@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | cap 10[40] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | ASPM disabled(L0s) | ||
+ | none5@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | cap 10[40] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | ASPM disabled(L0s) | ||
+ | none6@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | cap 10[40] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | ASPM disabled(L0s) | ||
+ | none7@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | ioapic0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | none8@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | bar [10] = type Memory, range 64, base 0x97d00000, size 16384, enabled | ||
+ | cap 11[80] = MSI-X supports 1 message in map 0x10 | ||
+ | cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D3 | ||
+ | none9@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | bar [10] = type Memory, range 64, base 0x97d04000, size 16384, enabled | ||
+ | cap 11[80] = MSI-X supports 1 message in map 0x10 | ||
+ | cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D3 | ||
+ | none10@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | bar [10] = type Memory, range 64, base 0x97d08000, size 16384, enabled | ||
+ | cap 11[80] = MSI-X supports 1 message in map 0x10 | ||
+ | cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D3 | ||
+ | none11@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | bar [10] = type Memory, range 64, base 0x97d0c000, size 16384, enabled | ||
+ | cap 11[80] = MSI-X supports 1 message in map 0x10 | ||
+ | cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D3 | ||
+ | none12@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | bar [10] = type Memory, range 64, base 0x97d10000, size 16384, enabled | ||
+ | cap 11[80] = MSI-X supports 1 message in map 0x10 | ||
+ | cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D3 | ||
+ | none13@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | bar [10] = type Memory, range 64, base 0x97d14000, size 16384, enabled | ||
+ | cap 11[80] = MSI-X supports 1 message in map 0x10 | ||
+ | cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D3 | ||
+ | none14@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | bar [10] = type Memory, range 64, base 0x97d18000, size 16384, enabled | ||
+ | cap 11[80] = MSI-X supports 1 message in map 0x10 | ||
+ | cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D3 | ||
+ | none15@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | bar [10] = type Memory, range 64, base 0x97d1c000, size 16384, enabled | ||
+ | cap 11[80] = MSI-X supports 1 message in map 0x10 | ||
+ | cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D3 | ||
+ | uhci0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = serial bus | ||
+ | subclass | ||
+ | bar [20] = type I/O Port, range 32, base 0x20a0, size 32, enabled | ||
+ | cap 13[50] = PCI Advanced Features: FLR TP | ||
+ | uhci1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = serial bus | ||
+ | subclass | ||
+ | bar [20] = type I/O Port, range 32, base 0x2080, size 32, enabled | ||
+ | cap 13[50] = PCI Advanced Features: FLR TP | ||
+ | ehci0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = serial bus | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 32, base 0x97d21000, size 1024, enabled | ||
+ | cap 01[50] = powerspec 2 supports D0 D3 current D0 | ||
+ | cap 0a[58] = EHCI Debug Port at offset 0xa0 in map 0x14 | ||
+ | cap 13[98] = PCI Advanced Features: FLR TP | ||
+ | pcib5@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 10[40] = PCI-Express 1 root port slot max data 128(128) link x4(x4) | ||
+ | speed 2.5(2.5) | ||
+ | cap 05[80] = MSI supports 1 message | ||
+ | cap 0d[90] = PCI Bridge card=0x3a401014 | ||
+ | cap 01[a0] = powerspec 2 supports D0 D3 current D0 | ||
+ | ecap 0002[100] = VC 1 max VC0 | ||
+ | ecap 0005[180] = Root Complex Link Declaration 1 | ||
+ | pcib6@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 10[40] = PCI-Express 1 root port max data 128(128) link x1(x1) | ||
+ | speed 2.5(2.5) | ||
+ | cap 05[80] = MSI supports 1 message | ||
+ | cap 0d[90] = PCI Bridge card=0x3a481014 | ||
+ | cap 01[a0] = powerspec 2 supports D0 D3 current D0 | ||
+ | ecap 0002[100] = VC 1 max VC0 | ||
+ | ecap 0005[180] = Root Complex Link Declaration 1 | ||
+ | uhci2@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = serial bus | ||
+ | subclass | ||
+ | bar [20] = type I/O Port, range 32, base 0x2060, size 32, enabled | ||
+ | cap 13[50] = PCI Advanced Features: FLR TP | ||
+ | uhci3@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = serial bus | ||
+ | subclass | ||
+ | bar [20] = type I/O Port, range 32, base 0x2040, size 32, enabled | ||
+ | cap 13[50] = PCI Advanced Features: FLR TP | ||
+ | uhci4@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = serial bus | ||
+ | subclass | ||
+ | bar [20] = type I/O Port, range 32, base 0x2020, size 32, enabled | ||
+ | cap 13[50] = PCI Advanced Features: FLR TP | ||
+ | ehci1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = serial bus | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 32, base 0x97d20000, size 1024, enabled | ||
+ | cap 01[50] = powerspec 2 supports D0 D3 current D0 | ||
+ | cap 0a[58] = EHCI Debug Port at offset 0xa0 in map 0x14 | ||
+ | cap 13[98] = PCI Advanced Features: FLR TP | ||
+ | pcib8@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 0d[50] = PCI Bridge card=0x244e1014 | ||
+ | isab0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 09[e0] = vendor (length 12) Intel cap 1 version 0 | ||
+ | | ||
+ | atapci0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = mass storage | ||
+ | subclass | ||
+ | bar [10] = type I/O Port, range 32, base 0x2118, size 8, enabled | ||
+ | bar [14] = type I/O Port, range 32, base 0x212c, size 4, enabled | ||
+ | bar [18] = type I/O Port, range 32, base 0x2110, size 8, enabled | ||
+ | bar [1c] = type I/O Port, range 32, base 0x2128, size 4, enabled | ||
+ | bar [20] = type I/O Port, range 32, base 0x20f0, size 16, enabled | ||
+ | bar [24] = type I/O Port, range 32, base 0x20e0, size 16, enabled | ||
+ | cap 01[70] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 13[b0] = PCI Advanced Features: FLR TP | ||
+ | ichsmb0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = serial bus | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 64, base 0x97d22000, size 256, enabled | ||
+ | bar [20] = type I/O Port, range 32, base 0x2000, size 32, enabled | ||
+ | atapci1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = mass storage | ||
+ | subclass | ||
+ | bar [10] = type I/O Port, range 32, base 0x2108, size 8, enabled | ||
+ | bar [14] = type I/O Port, range 32, base 0x2124, size 4, enabled | ||
+ | bar [18] = type I/O Port, range 32, base 0x2100, size 8, enabled | ||
+ | bar [1c] = type I/O Port, range 32, base 0x2120, size 4, enabled | ||
+ | bar [20] = type I/O Port, range 32, base 0x20d0, size 16, enabled | ||
+ | bar [24] = type I/O Port, range 32, base 0x20c0, size 16, enabled | ||
+ | cap 01[70] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 13[b0] = PCI Advanced Features: FLR TP | ||
+ | bce0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = network | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 64, base 0x92000000, size 33554432, enabled | ||
+ | cap 01[48] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 03[50] = VPD | ||
+ | cap 05[58] = MSI supports 16 messages, 64 bit enabled with 1 message | ||
+ | cap 11[a0] = MSI-X supports 9 messages in map 0x10 | ||
+ | cap 10[ac] = PCI-Express 2 endpoint max data 256(512) link x2(x4) | ||
+ | speed 5.0(5.0) ASPM disabled(L0s/ | ||
+ | ecap 0003[100] = Serial 1 5cf3fcfffee5a2f8 | ||
+ | ecap 0001[110] = AER 1 0 fatal 0 non-fatal 1 corrected | ||
+ | ecap 0004[150] = Power Budgeting 1 | ||
+ | ecap 0002[160] = VC 1 max VC0 | ||
+ | bce1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = network | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 64, base 0x94000000, size 33554432, enabled | ||
+ | cap 01[48] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 03[50] = VPD | ||
+ | cap 05[58] = MSI supports 16 messages, 64 bit enabled with 1 message | ||
+ | cap 11[a0] = MSI-X supports 9 messages in map 0x10 | ||
+ | cap 10[ac] = PCI-Express 2 endpoint max data 256(512) link x2(x4) | ||
+ | speed 5.0(5.0) ASPM disabled(L0s/ | ||
+ | ecap 0003[100] = Serial 1 5cf3fcfffee5a2fa | ||
+ | ecap 0001[110] = AER 1 0 fatal 0 non-fatal 1 corrected | ||
+ | ecap 0004[150] = Power Budgeting 1 | ||
+ | ecap 0002[160] = VC 1 max VC0 | ||
+ | ix0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = network | ||
+ | subclass | ||
+ | bar [10] = type Prefetchable Memory, range 64, base 0xfbc00000, size 2097152, enabled | ||
+ | bar [20] = type Prefetchable Memory, range 64, base 0xfbe04000, size 16384, enabled | ||
+ | cap 01[40] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 05[50] = MSI supports 1 message, 64 bit, vector masks | ||
+ | cap 11[70] = MSI-X supports 64 messages in map 0x20 enabled | ||
+ | cap 10[a0] = PCI-Express 2 endpoint max data 256(512) FLR link x8(x8) | ||
+ | speed 5.0(5.0) ASPM disabled(L0s/ | ||
+ | ecap 0001[100] = AER 2 0 fatal 0 non-fatal 1 corrected | ||
+ | ecap 0003[140] = Serial 1 a0369fffff1e1ed8 | ||
+ | ecap 000e[150] = ARI 1 | ||
+ | ecap 0010[160] = SRIOV 1 | ||
+ | ecap 000d[1d0] = ACS 1 | ||
+ | ix1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = network | ||
+ | subclass | ||
+ | bar [10] = type Prefetchable Memory, range 64, base 0xfba00000, size 2097152, enabled | ||
+ | bar [20] = type Prefetchable Memory, range 64, base 0xfbe00000, size 16384, enabled | ||
+ | cap 01[40] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 05[50] = MSI supports 1 message, 64 bit, vector masks | ||
+ | cap 11[70] = MSI-X supports 64 messages in map 0x20 enabled | ||
+ | cap 10[a0] = PCI-Express 2 endpoint max data 256(512) FLR link x8(x8) | ||
+ | speed 5.0(5.0) ASPM disabled(L0s/ | ||
+ | ecap 0001[100] = AER 2 0 fatal 0 non-fatal 1 corrected | ||
+ | ecap 0003[140] = Serial 1 a0369fffff1e1ed8 | ||
+ | ecap 000e[150] = ARI 1 | ||
+ | ecap 0010[160] = SRIOV 1 | ||
+ | ecap 000d[1d0] = ACS 1 | ||
+ | igb0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = network | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 32, base 0x97b80000, size 524288, enabled | ||
+ | bar [1c] = type Memory, range 32, base 0x97c0c000, size 16384, enabled | ||
+ | cap 01[40] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 05[50] = MSI supports 1 message, 64 bit, vector masks | ||
+ | cap 11[70] = MSI-X supports 10 messages in map 0x1c enabled | ||
+ | cap 10[a0] = PCI-Express 2 endpoint max data 256(512) FLR link x4(x4) | ||
+ | speed 5.0(5.0) ASPM disabled(L0s/ | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 1 corrected | ||
+ | ecap 0003[140] = Serial 1 001b21ffffd43f28 | ||
+ | ecap 0017[1a0] = TPH Requester 1 | ||
+ | ecap 0018[1c0] = LTR 1 | ||
+ | igb1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = network | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 32, base 0x97b00000, size 524288, enabled | ||
+ | bar [1c] = type Memory, range 32, base 0x97c08000, size 16384, enabled | ||
+ | cap 01[40] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 05[50] = MSI supports 1 message, 64 bit, vector masks | ||
+ | cap 11[70] = MSI-X supports 10 messages in map 0x1c enabled | ||
+ | cap 10[a0] = PCI-Express 2 endpoint max data 256(512) FLR link x4(x4) | ||
+ | speed 5.0(5.0) ASPM disabled(L0s/ | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 1 corrected | ||
+ | ecap 0003[140] = Serial 1 001b21ffffd43f28 | ||
+ | ecap 0017[1a0] = TPH Requester 1 | ||
+ | igb2@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = network | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 32, base 0x97a80000, size 524288, enabled | ||
+ | bar [1c] = type Memory, range 32, base 0x97c04000, size 16384, enabled | ||
+ | cap 01[40] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 05[50] = MSI supports 1 message, 64 bit, vector masks | ||
+ | cap 11[70] = MSI-X supports 10 messages in map 0x1c enabled | ||
+ | cap 10[a0] = PCI-Express 2 endpoint max data 256(512) FLR link x4(x4) | ||
+ | speed 5.0(5.0) ASPM disabled(L0s/ | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 1 corrected | ||
+ | ecap 0003[140] = Serial 1 001b21ffffd43f28 | ||
+ | ecap 0017[1a0] = TPH Requester 1 | ||
+ | igb3@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = network | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 32, base 0x97a00000, size 524288, enabled | ||
+ | bar [1c] = type Memory, range 32, base 0x97c00000, size 16384, enabled | ||
+ | cap 01[40] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 05[50] = MSI supports 1 message, 64 bit, vector masks | ||
+ | cap 11[70] = MSI-X supports 10 messages in map 0x1c enabled | ||
+ | cap 10[a0] = PCI-Express 2 endpoint max data 256(512) FLR link x4(x4) | ||
+ | speed 5.0(5.0) ASPM disabled(L0s/ | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 1 corrected | ||
+ | ecap 0003[140] = Serial 1 001b21ffffd43f28 | ||
+ | ecap 0017[1a0] = TPH Requester 1 | ||
+ | mpt0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = mass storage | ||
+ | subclass | ||
+ | bar [10] = type I/O Port, range 32, base 0x1000, size 256, disabled | ||
+ | bar [14] = type Memory, range 64, base 0x97910000, size 16384, enabled | ||
+ | bar [1c] = type Memory, range 64, base 0x97900000, size 65536, enabled | ||
+ | cap 01[50] = powerspec 2 supports D0 D1 D2 D3 current D0 | ||
+ | cap 10[68] = PCI-Express 1 endpoint max data 128(4096) link x4(x8) | ||
+ | speed 2.5(2.5) ASPM disabled(L0s/ | ||
+ | cap 05[98] = MSI supports 1 message, 64 bit | ||
+ | cap 11[b0] = MSI-X supports 1 message in map 0x14 enabled | ||
+ | ecap 0001[100] = AER 1 0 fatal 1 non-fatal 0 corrected | ||
+ | pcib7@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 05[50] = MSI supports 2 messages, 64 bit | ||
+ | cap 01[78] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 10[80] = PCI-Express 1 PCI bridge max data 128(128) link x1(x1) | ||
+ | speed 2.5(2.5) ASPM disabled(L0s) | ||
+ | cap 0d[a4] = PCI Bridge card=0x03691014 | ||
+ | ecap 0002[100] = VC 1 max VC0 | ||
+ | vgapci0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = display | ||
+ | subclass | ||
+ | bar [10] = type Prefetchable Memory, range 32, base 0x96000000, size 16777216, enabled | ||
+ | bar [14] = type Memory, range 32, base 0x97800000, size 16384, enabled | ||
+ | bar [18] = type Memory, range 32, base 0x97000000, size 8388608, enabled | ||
+ | cap 01[dc] = powerspec 1 supports D0 D3 current D0 | ||
+ | hostb1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb2@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb3@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb4@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb5@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb6@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb7@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb8@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb9@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb10@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb11@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb12@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb13@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb14@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb15@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb16@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb17@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb18@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb19@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb20@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb21@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb22@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb23@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb24@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | |||
+ | |||
+ | |||
+ | |||
+ | |||
+ | [root@bsdrp1]~# | ||
+ | hostb0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 05[60] = MSI supports 2 messages, vector masks | ||
+ | cap 10[90] = PCI-Express 2 root port max data 128(128) link x4(x4) | ||
+ | speed 2.5(2.5) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D0 | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 0 corrected | ||
+ | ecap 000d[150] = ACS 1 | ||
+ | ecap 000b[160] = Vendor 0 | ||
+ | pcib1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 0d[40] = PCI Bridge card=0x34081014 | ||
+ | cap 05[60] = MSI supports 2 messages, vector masks | ||
+ | cap 10[90] = PCI-Express 2 root port max data 256(256) link x2(x2) | ||
+ | speed 5.0(5.0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D0 | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 0 corrected | ||
+ | ecap 000d[150] = ACS 1 | ||
+ | ecap 000b[160] = Vendor 0 | ||
+ | pcib2@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 0d[40] = PCI Bridge card=0x34091014 | ||
+ | cap 05[60] = MSI supports 2 messages, vector masks | ||
+ | cap 10[90] = PCI-Express 2 root port max data 256(256) link x0(x2) | ||
+ | speed 0.0(5.0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D0 | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 0 corrected | ||
+ | ecap 000d[150] = ACS 1 | ||
+ | pcib3@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 0d[40] = PCI Bridge card=0x340a1014 | ||
+ | cap 05[60] = MSI supports 2 messages, vector masks | ||
+ | cap 10[90] = PCI-Express 2 root port slot max data 256(256) link x0(x16) | ||
+ | speed 0.0(5.0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D0 | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 0 corrected | ||
+ | ecap 000d[150] = ACS 1 | ||
+ | ecap 000b[160] = Vendor 0 | ||
+ | pcib4@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 0d[40] = PCI Bridge card=0x340e1014 | ||
+ | cap 05[60] = MSI supports 2 messages, vector masks | ||
+ | cap 10[90] = PCI-Express 2 root port slot max data 256(256) link x4(x16) | ||
+ | speed 5.0(5.0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D0 | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 0 corrected | ||
+ | ecap 000d[150] = ACS 1 | ||
+ | ecap 000b[160] = Vendor 0 | ||
+ | none0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | cap 09[50] = vendor (length 255) Intel cap 15 version 0 | ||
+ | none1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | none2@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | cap 09[50] = vendor (length 255) Intel cap 15 version 0 | ||
+ | none3@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | none4@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | cap 10[40] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | none5@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | cap 10[40] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | none6@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | cap 10[40] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | none7@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | ioapic0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | subclass | ||
+ | none8@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | bar [10] = type Memory, range 64, base 0x97d00000, size 16384, enabled | ||
+ | cap 11[80] = MSI-X supports 1 message in map 0x10 | ||
+ | cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D3 | ||
+ | none9@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | bar [10] = type Memory, range 64, base 0x97d04000, size 16384, enabled | ||
+ | cap 11[80] = MSI-X supports 1 message in map 0x10 | ||
+ | cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D3 | ||
+ | none10@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | bar [10] = type Memory, range 64, base 0x97d08000, size 16384, enabled | ||
+ | cap 11[80] = MSI-X supports 1 message in map 0x10 | ||
+ | cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D3 | ||
+ | none11@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | bar [10] = type Memory, range 64, base 0x97d0c000, size 16384, enabled | ||
+ | cap 11[80] = MSI-X supports 1 message in map 0x10 | ||
+ | cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D3 | ||
+ | none12@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | bar [10] = type Memory, range 64, base 0x97d10000, size 16384, enabled | ||
+ | cap 11[80] = MSI-X supports 1 message in map 0x10 | ||
+ | cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D3 | ||
+ | none13@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | bar [10] = type Memory, range 64, base 0x97d14000, size 16384, enabled | ||
+ | cap 11[80] = MSI-X supports 1 message in map 0x10 | ||
+ | cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D3 | ||
+ | none14@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | bar [10] = type Memory, range 64, base 0x97d18000, size 16384, enabled | ||
+ | cap 11[80] = MSI-X supports 1 message in map 0x10 | ||
+ | cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D3 | ||
+ | none15@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = base peripheral | ||
+ | bar [10] = type Memory, range 64, base 0x97d1c000, size 16384, enabled | ||
+ | cap 11[80] = MSI-X supports 1 message in map 0x10 | ||
+ | cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) | ||
+ | cap 01[e0] = powerspec 3 supports D0 D3 current D3 | ||
+ | uhci0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = serial bus | ||
+ | subclass | ||
+ | bar [20] = type I/O Port, range 32, base 0x20a0, size 32, enabled | ||
+ | cap 13[50] = PCI Advanced Features: FLR TP | ||
+ | uhci1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = serial bus | ||
+ | subclass | ||
+ | bar [20] = type I/O Port, range 32, base 0x2080, size 32, enabled | ||
+ | cap 13[50] = PCI Advanced Features: FLR TP | ||
+ | ehci0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = serial bus | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 32, base 0x97d21000, size 1024, enabled | ||
+ | cap 01[50] = powerspec 2 supports D0 D3 current D0 | ||
+ | cap 0a[58] = EHCI Debug Port at offset 0xa0 in map 0x14 | ||
+ | cap 13[98] = PCI Advanced Features: FLR TP | ||
+ | pcib5@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 10[40] = PCI-Express 1 root port slot max data 128(128) link x4(x4) | ||
+ | speed 2.5(2.5) | ||
+ | cap 05[80] = MSI supports 1 message | ||
+ | cap 0d[90] = PCI Bridge card=0x3a401014 | ||
+ | cap 01[a0] = powerspec 2 supports D0 D3 current D0 | ||
+ | ecap 0002[100] = VC 1 max VC0 | ||
+ | ecap 0005[180] = Root Complex Link Declaration 1 | ||
+ | pcib6@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 10[40] = PCI-Express 1 root port max data 128(128) link x1(x1) | ||
+ | speed 2.5(2.5) | ||
+ | cap 05[80] = MSI supports 1 message | ||
+ | cap 0d[90] = PCI Bridge card=0x3a481014 | ||
+ | cap 01[a0] = powerspec 2 supports D0 D3 current D0 | ||
+ | ecap 0002[100] = VC 1 max VC0 | ||
+ | ecap 0005[180] = Root Complex Link Declaration 1 | ||
+ | uhci2@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = serial bus | ||
+ | subclass | ||
+ | bar [20] = type I/O Port, range 32, base 0x2060, size 32, enabled | ||
+ | cap 13[50] = PCI Advanced Features: FLR TP | ||
+ | uhci3@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = serial bus | ||
+ | subclass | ||
+ | bar [20] = type I/O Port, range 32, base 0x2040, size 32, enabled | ||
+ | cap 13[50] = PCI Advanced Features: FLR TP | ||
+ | uhci4@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = serial bus | ||
+ | subclass | ||
+ | bar [20] = type I/O Port, range 32, base 0x2020, size 32, enabled | ||
+ | cap 13[50] = PCI Advanced Features: FLR TP | ||
+ | ehci1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = serial bus | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 32, base 0x97d20000, size 1024, enabled | ||
+ | cap 01[50] = powerspec 2 supports D0 D3 current D0 | ||
+ | cap 0a[58] = EHCI Debug Port at offset 0xa0 in map 0x14 | ||
+ | cap 13[98] = PCI Advanced Features: FLR TP | ||
+ | pcib8@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 0d[50] = PCI Bridge card=0x244e1014 | ||
+ | isab0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 09[e0] = vendor (length 12) Intel cap 1 version 0 | ||
+ | | ||
+ | atapci0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = mass storage | ||
+ | subclass | ||
+ | bar [10] = type I/O Port, range 32, base 0x2118, size 8, enabled | ||
+ | bar [14] = type I/O Port, range 32, base 0x212c, size 4, enabled | ||
+ | bar [18] = type I/O Port, range 32, base 0x2110, size 8, enabled | ||
+ | bar [1c] = type I/O Port, range 32, base 0x2128, size 4, enabled | ||
+ | bar [20] = type I/O Port, range 32, base 0x20f0, size 16, enabled | ||
+ | bar [24] = type I/O Port, range 32, base 0x20e0, size 16, enabled | ||
+ | cap 01[70] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 13[b0] = PCI Advanced Features: FLR TP | ||
+ | ichsmb0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = serial bus | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 64, base 0x97d22000, size 256, enabled | ||
+ | bar [20] = type I/O Port, range 32, base 0x2000, size 32, enabled | ||
+ | atapci1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = mass storage | ||
+ | subclass | ||
+ | bar [10] = type I/O Port, range 32, base 0x2108, size 8, enabled | ||
+ | bar [14] = type I/O Port, range 32, base 0x2124, size 4, enabled | ||
+ | bar [18] = type I/O Port, range 32, base 0x2100, size 8, enabled | ||
+ | bar [1c] = type I/O Port, range 32, base 0x2120, size 4, enabled | ||
+ | bar [20] = type I/O Port, range 32, base 0x20d0, size 16, enabled | ||
+ | bar [24] = type I/O Port, range 32, base 0x20c0, size 16, enabled | ||
+ | cap 01[70] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 13[b0] = PCI Advanced Features: FLR TP | ||
+ | bce0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = network | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 64, base 0x92000000, size 33554432, enabled | ||
+ | cap 01[48] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 03[50] = VPD | ||
+ | cap 05[58] = MSI supports 16 messages, 64 bit enabled with 1 message | ||
+ | cap 11[a0] = MSI-X supports 9 messages in map 0x10 | ||
+ | cap 10[ac] = PCI-Express 2 endpoint max data 256(512) link x2(x4) | ||
+ | speed 5.0(5.0) | ||
+ | ecap 0003[100] = Serial 1 5cf3fcfffee5a2f8 | ||
+ | ecap 0001[110] = AER 1 0 fatal 0 non-fatal 1 corrected | ||
+ | ecap 0004[150] = Power Budgeting 1 | ||
+ | ecap 0002[160] = VC 1 max VC0 | ||
+ | bce1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = network | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 64, base 0x94000000, size 33554432, enabled | ||
+ | cap 01[48] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 03[50] = VPD | ||
+ | cap 05[58] = MSI supports 16 messages, 64 bit enabled with 1 message | ||
+ | cap 11[a0] = MSI-X supports 9 messages in map 0x10 | ||
+ | cap 10[ac] = PCI-Express 2 endpoint max data 256(512) link x2(x4) | ||
+ | speed 5.0(5.0) | ||
+ | ecap 0003[100] = Serial 1 5cf3fcfffee5a2fa | ||
+ | ecap 0001[110] = AER 1 0 fatal 0 non-fatal 1 corrected | ||
+ | ecap 0004[150] = Power Budgeting 1 | ||
+ | ecap 0002[160] = VC 1 max VC0 | ||
+ | igb0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = network | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 32, base 0x97b80000, size 524288, enabled | ||
+ | bar [1c] = type Memory, range 32, base 0x97c0c000, size 16384, enabled | ||
+ | cap 01[40] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 05[50] = MSI supports 1 message, 64 bit, vector masks | ||
+ | cap 11[70] = MSI-X supports 10 messages in map 0x1c enabled | ||
+ | cap 10[a0] = PCI-Express 2 endpoint max data 256(512) FLR link x4(x4) | ||
+ | speed 5.0(5.0) | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 1 corrected | ||
+ | ecap 0003[140] = Serial 1 001b21ffffd43f28 | ||
+ | ecap 0017[1a0] = TPH Requester 1 | ||
+ | ecap 0018[1c0] = LTR 1 | ||
+ | igb1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = network | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 32, base 0x97b00000, size 524288, enabled | ||
+ | bar [1c] = type Memory, range 32, base 0x97c08000, size 16384, enabled | ||
+ | cap 01[40] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 05[50] = MSI supports 1 message, 64 bit, vector masks | ||
+ | cap 11[70] = MSI-X supports 10 messages in map 0x1c enabled | ||
+ | cap 10[a0] = PCI-Express 2 endpoint max data 256(512) FLR link x4(x4) | ||
+ | speed 5.0(5.0) | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 1 corrected | ||
+ | ecap 0003[140] = Serial 1 001b21ffffd43f28 | ||
+ | ecap 0017[1a0] = TPH Requester 1 | ||
+ | igb2@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = network | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 32, base 0x97a80000, size 524288, enabled | ||
+ | bar [1c] = type Memory, range 32, base 0x97c04000, size 16384, enabled | ||
+ | cap 01[40] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 05[50] = MSI supports 1 message, 64 bit, vector masks | ||
+ | cap 11[70] = MSI-X supports 10 messages in map 0x1c enabled | ||
+ | cap 10[a0] = PCI-Express 2 endpoint max data 256(512) FLR link x4(x4) | ||
+ | speed 5.0(5.0) | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 1 corrected | ||
+ | ecap 0003[140] = Serial 1 001b21ffffd43f28 | ||
+ | ecap 0017[1a0] = TPH Requester 1 | ||
+ | igb3@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = network | ||
+ | subclass | ||
+ | bar [10] = type Memory, range 32, base 0x97a00000, size 524288, enabled | ||
+ | bar [1c] = type Memory, range 32, base 0x97c00000, size 16384, enabled | ||
+ | cap 01[40] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 05[50] = MSI supports 1 message, 64 bit, vector masks | ||
+ | cap 11[70] = MSI-X supports 10 messages in map 0x1c enabled | ||
+ | cap 10[a0] = PCI-Express 2 endpoint max data 256(512) FLR link x4(x4) | ||
+ | speed 5.0(5.0) | ||
+ | ecap 0001[100] = AER 1 0 fatal 0 non-fatal 1 corrected | ||
+ | ecap 0003[140] = Serial 1 001b21ffffd43f28 | ||
+ | ecap 0017[1a0] = TPH Requester 1 | ||
+ | mpt0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = mass storage | ||
+ | subclass | ||
+ | bar [10] = type I/O Port, range 32, base 0x1000, size 256, disabled | ||
+ | bar [14] = type Memory, range 64, base 0x97910000, size 16384, enabled | ||
+ | bar [1c] = type Memory, range 64, base 0x97900000, size 65536, enabled | ||
+ | cap 01[50] = powerspec 2 supports D0 D1 D2 D3 current D0 | ||
+ | cap 10[68] = PCI-Express 1 endpoint max data 128(4096) link x4(x8) | ||
+ | speed 2.5(2.5) | ||
+ | cap 05[98] = MSI supports 1 message, 64 bit | ||
+ | cap 11[b0] = MSI-X supports 1 message in map 0x14 enabled | ||
+ | ecap 0001[100] = AER 1 0 fatal 1 non-fatal 0 corrected | ||
+ | pcib7@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | cap 05[50] = MSI supports 2 messages, 64 bit | ||
+ | cap 01[78] = powerspec 3 supports D0 D3 current D0 | ||
+ | cap 10[80] = PCI-Express 1 PCI bridge max data 128(128) link x1(x1) | ||
+ | speed 2.5(2.5) | ||
+ | cap 0d[a4] = PCI Bridge card=0x03691014 | ||
+ | ecap 0002[100] = VC 1 max VC0 | ||
+ | vgapci0@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = display | ||
+ | subclass | ||
+ | bar [10] = type Prefetchable Memory, range 32, base 0x96000000, size 16777216, enabled | ||
+ | bar [14] = type Memory, range 32, base 0x97800000, size 16384, enabled | ||
+ | bar [18] = type Memory, range 32, base 0x97000000, size 8388608, enabled | ||
+ | cap 01[dc] = powerspec 1 supports D0 D3 current D0 | ||
+ | hostb1@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb2@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb3@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb4@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb5@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb6@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb7@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb8@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb9@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb10@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb11@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb12@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb13@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb14@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb15@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb16@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb17@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb18@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb19@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb20@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb21@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb22@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb23@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | hostb24@pci0: | ||
+ | vendor | ||
+ | device | ||
+ | class = bridge | ||
+ | subclass | ||
+ | |||
+ | </ |
documentation/examples/ibm_system_x3550_m3.txt · Last modified: 2013/09/19 22:20 by 127.0.0.1